In practice, a distinction is made between dynamic, clocked static and non-clocked static memory cells. Dynamic memory cells consume a minimum of space and thus are easy to produce at low cost. A disadvantage is, however, that refresh cycles have to be performed within a rigid time pattern. Typical applications of such cells are main memories of computer systems and video refresh buffers of high-resolution graphic displays. For such applications, the periodically recurring refresh cycles can easily be masked. Where this is not possible, as, for instance, in cache, direct-look-aside table (DLAT) or data local store (DLS) memories, clocked static or non-clocked static cells, that are much more elaborate, have to be used.
Cache memories, containing portions of the main program that are currently processed by a central processing unit (CPU), are used as high-speed buffers between the slower main memory of a computer system and the CPU. Although their capacity is limited in most cases, such memories must be very fast and access to them should not be interrupted by refresh cycles, etc. As the CPU directly communicates with the cache memories, the data processing speed is directly dependent on the latter. In state-of-the-art microprocessor designs, such memories are frequently integrated on the chip (embedded arrays), so that, in addition to the access time, the power requirements are a critical parameter. DLAT memories, which are often organized to have a large word length but a limited capacity, contain the conversion tables employed in virtual storage concepts for generating the physical addresses. As DLAT memories are used to compute both the cache and the main memory addresses, the data processing speed of the CPU is directly dependent on them. The same holds for DLSs storing the microcode for instruction generation.
As clocked static memories, viewed from the periphery, have to be controlled within a rigid time pattern (requiring, for example, signals indicating when addresses and data are stable), the use of memories with non-clocked static cells is indispensable for many applications, such as the above-mentioned embedded arrays in complex very large scale integrated (VLSI) chips. Save for the finite access time, the operation of the latter type of memories is not limited with respect to time characteristics.
Non-clocked static memory cells are known. IBM Technical Disclosure Bulletin, Vol. 17, No. 11, April 1975, pp. 3338-3339, describes the concept of a non-clocked static memory cell realized as a 6-transistor CMOS cell with two bit lines and one word line.
A memory array thus designed has the disadvantage that DC current is drawn by all cells of a selected word line. A further DC current path extend across the sense amplifier. Therefore, a memory array designed to that circuit concept has high power requirements compared with clocked memory arrays, particularly if the word length is large, i.e., if a large number of cells are associated with one word line.
Because of the low gain factor of differential field effect transistor (FET) amplifiers, a two-stage sense amplifier is required for reading the memory content, thus leading to increased access times.
A further disadvantage of known circuit concepts, also with respect to clocked static memories, is the risk of double selection of memory cells in response to address changes, and of erroneous changes of the cell content under the influence of the bit line capacity, which has to be remedied in each case by additional peripheral circuits.
An embodiment of a non-clocked static memory cell preventing "cross-talk" between the bit line and the cell is described by U. Baitinger et al, in IBM Technical Disclosure Bulletin, Vol. 14, No. 12, 1972, pp. 3640-3641. However, that concept does not solve the problem of high power requirements and slow sense amplifiers.